1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and a manufacturing method for the same and, more particularly, to a semiconductor integrated circuit device having an SOI (silicon on insulator) structure to realize with electrical stability a structure formed together with a semiconductor element having a pn-junction in a semiconductor substrate and a manufacturing method for the same.
2. Description of Related Art
As is well-known, when formed with a semiconductor element at a silicon layer formed on a semiconductor substrate through an insulating film, or at an SOI layer, a semiconductor integrated circuit device can be built with reduced parasitic capacity of the elements, thereby improving its performance, such as high speed and low power consumption. Meanwhile, such a semiconductor integrated circuit device with the SOI structure may be required to be formed with a semiconductor element having a pn-junction in the semiconductor substrate. For example, Japanese Laid-Open Patent Publication No. Hei 4-345064 discloses an example in which a protection circuit element is formed in the semiconductor substrate to protect the semiconductor integrated circuit device when a high voltage is applied due to static electricity or like from the outside of the semiconductor integrated circuit device.
FIG. 7 shows a cross-sectional structure of the essential portion of the semiconductor integrated circuit device having such an SOI structure formed with a semiconductor element having a pn-junction in the semiconductor substrate. FIG. 8 shows an equivalent circuit of the semiconductor integrated circuit device shown in FIG. 7. With the semiconductor integrated circuit device shown in FIG. 7, a semiconductor substrate 1 is made of, e.g., a p-type silicon single-crystal substrate, on which a buried insulating film 2 made of, e.g., SiO.sub.2 is formed. Single-crystal silicon layers isolated in a fashion to form islands, or SOI layers 3 (3A and 3B) are formed on the buried insulating film 2, thereby realizing the SOI structure as a semiconductor integrated circuit device. An isolating insulating film 4 made of, e.g., SiO.sub.2 is formed around the SOI layers 3A, 3B when necessary.
In the semiconductor integrated circuit device, an n-channel MOSFET 9A is constituted at the SOI layer 3A by a source region 5A and a drain region 6A formed therein, a gate insulating film 7A formed on the SOI layer 3A, and a gate electrode 8A made of, e.g., polysilicon on the gate insulating film 7A. Similarly, a p-channel MOSFET 9B is constituted at the SOI layer 3B by a source region 5B and a drain region 6B, a gate insulating film 7B on the SOI layer 3B, and a gate electrode 8B on the gate insulating film 7B. An interlayer insulating film 10 is formed on the SOI layers 3A, 3B and the isolating insulating film 4, and interconnections 12 made of, e.g., aluminum (Al) alloy are formed as to contact with the source regions 5, the drain regions 6, and the gate electrodes 8, though contacting portions are not shown, of the MOSFETs 9A, 9B, respectively, through contact holes 11 opened in the interlayer insulating film 10.
By means of the interconnections 12, the source region 5A of the n-channel MOSFET 9A is coupled to a ground line Vss, and the source region 5B of the p-channel MOSFET 9B is coupled to a power supply line Vdd. A CMOS inverter circuit 101 shown in FIG. 8 is constituted of the n-channel and p-channel MOSFETs 9A and 9B. It is to be noted that in the semiconductor integrated circuit device, as shown in FIG. 8, the CMOS inverter circuit 101 is used as an input circuit. Formed between a bonding pad 102 serving as a connecting terminal for an external device and the CMOS inverter circuit 101 is an input protection circuit 103 for protecting the CMOS inverter circuit 101. The input protection circuit 103 is constituted of a protection resistor 13 inserted serially between the bonding pad 102 and the CMOS inverter circuit 101 and a protection transistor 14 serially connected between the input of the CMOS inverter circuit 101 and the ground line Vss. As the protection transistor 14, e.g., an n-channel MOSFET is used.
Referring to FIG. 7, the structure of the protection transistor 14 constituted as the n-channel MOSFET is described. In the semiconductor integrated circuit device shown in FIG. 7, the protection transistor 14 is constituted of source and drain regions 15, 16 made of n-type diffusion layers formed in the p-type semiconductor substrate 1, a gate insulating film 17 formed on the semiconductor substrate 1, and a gate electrode 18 formed on the gate insulating film 17. The gate insulating film 17 is a part of the buried insulating film 2, and the gate electrode 18 is a part of the SOI layer 3. In the protection transistor 14 thus constituted, interconnections 12 made of, e.g., aluminum alloy are connected with the source and drain regions 15, 16 through contact holes 11C. The contact holes 11C are formed to open the interlayer insulating film 10 deposited so as to bury the substrate contact holes 11B formed to open the buried insulating film 2 (the gate insulating film 17) as well as the SOI layer 3 (the gate electrode 18). Another interconnection 12, though not shown, is also connected to the gate electrode 18 through the contact hole 11C formed to open the interlayer insulating film 10. Moreover, in the semiconductor integrated circuit device shown in FIG. 7, a highly doped p-type diffusion layer 19 is formed in the p-type semiconductor substrate 1. The p-type diffusion layer 19 is a diffusion layer for electrically coupling the semiconductor substrate 1 with an interconnection 12D, so that the semiconductor substrate 1 is connected to, e.g., the ground line Vss through the p-type diffusion layer 19 and the interconnection 12D. Thus, in the semiconductor integrated circuit device shown in FIGS. 7 and 8, the protection transistor 14 having a pn-junction in the semiconductor substrate 1 of the CMOS inverter circuit 101 is formed together with the SOI structure of the CMOS inverter circuit 101. Large current created due to static electricity can therefore be discharged to the semiconductor substrate 1 through the protection transistor 14, thereby preventing a large current from flowing directly into the CMOS inverter circuit 101. That is, the protection transistor 14 suitably prevents the CMOS inverter circuit 101 from being impaired or destroyed.
As described above, with the semiconductor integrated circuit device having the SOI structure, a semiconductor element having a pn-junction in the semiconductor substrate for protection of, e.g., other integrated circuit elements may be formed together with the SOI structure. With such a structure formed together with a semiconductor element having a pn-junction in the semiconductor substrate, however, it has been discovered by the inventor(s) that leak current may occur, e.g., between the n+ type diffusion layer and the p+-type diffusion layer or n+-type diffusion layer formed in the p-type semiconductor substrate.
That is, with the semiconductor integrated circuit device exemplified in FIG. 7, when a positive voltage with respect to the semiconductor substrate 1 is applied to the drain region 16 of the n-channel MOSFET constituting the protection transistor 14, leak current L1 or L2 as shown by arrows may occur around the interface between the semiconductor substrate 1 and the buried insulating film 2 (gate insulating film 17). Specifically, the leak current L1 flowing from the drain region 16 to the source region 17 is a current generated due to a low threshold voltage of the protection transistor 14 (which is turned into a depletion-type transistor). Even though the voltage applied to the gate electrode 18 is, e.g., zero volts, a channel is formed at the surface portion of the semiconductor substrate 1 between the drain and source regions 16, 15, thereby permitting the current L1 to flow. On the other hand, the leak current L2 flowing from the drain region 16 to the p-type diffusion layer 19 is a current generated due to formation of a depletion layer around the surface of the semiconductor substrate 1.
At any rate, when the leak current L1 or L2 thus occurs, even off-characteristics of the n-channel MOSFET constituting the protection transistor 14 are impaired significantly. Signal voltage from the outside leaked into other terminals through such elements may invite inconveniences such that normal signals are not transmitted to internal integrated circuit elements or that power consumption as a semiconductor integrated circuit device increases. It is to be noted that boron as p-type impurity tends to be absorbed in the SiO.sub.2 layer as the buried insulating film 2 from the silicon layer as the semiconductor substrate 1 by thermal treatment. Therefore, particularly when a p-type substrate is used as the semiconductor substrate 1, the impurity concentration is easily lowered around the interface between the semiconductor substrate 1 and the buried insulating film 2, thereby revealing such problems.